AI-enabled chips are revolutionizing computing with their unique architecture and capabilities. These specialized chips, including GPUs, FPGAs, and ASICs, are designed to handle the high data processing requirements of AI workloads. By leveraging parallel processing, large memory capacities, and energy efficiency, AI chips outperform general-purpose chips in tasks such as image recognition, natural language processing, and autonomous vehicles, unlocking new frontiers in artificial intelligence and shaping the future of technology.

Today, the finances and resources spent on research and development in robotics and automation technology have seen an exponential increase. With advancements in technology, we have seen the adoption of robots across various sectors including industrial, manufacturing, consumer, and many more. The adoption of highly efficient robots will also help in addressing the skilled labor shortage in near future.

To keep up the pace with Moore’s law, manufacturing technology

Effectively managing a huge pool of electronic parts from various

What is LVS? In ASIC physical implementation, once layout is

To begin with, Value Analysis and Value Engineering help in

The recent increase in the technology usage and the competition

Deep Learning has emerged as one of the most exciting

1. Introduction Effect of charge accumulation in isolated nodes of

The most disruptive megatrends impacting the ASIC networking industry today

In this era of pervasive connectivity, everything needs to communicate

Design for Testability (DFT), is one of the effective ways

The developments in the past in chip design laid the

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

Verification is the process of reviewing, inspecting, or testing hardware

While developing large-sized chips, “divide & conquer” techniques are used.

Typically, we see a 4X increase in memory size every

Over the years, we have seen a wide range of

The intent of this paper is to explain the varied

Nowadays, placing multiple IPs on a single chip plays the

With the advent of personal computers and integrated circuits, the

With advanced technology nodes, the SoCs are growing in density

Introduction The VLSI design cycle is divided into two phases:

The use of mixed-signal processing is becoming vital among a

Abstract Assertion is a very powerful feature of System Verilog

The ‘Semiconductor era’ started in 1960 with the invention of

In this day and age, we need sleeker devices with more capabilities and longer battery life. This can be accomplished by packing more components on smaller chips, thus moving to low geometry chip design. However, power dissipation or leakage current occurs in all the circuits that are currently used, which increases the overall power consumption, making it less suitable for mobile applications. This blog talks about the types of power dissipation and also mentions the ways to prevent this voltage loss.

In any physical design procedure, Placement and Routing are the

As consumer demand keeps changing, manufacturers need to change or upgrade their product to stay relevant. FPGAs are designed to provide the required flexibility and make changes to the device functionalities at any point even after deployment at the customers’ end. This blog will discuss how FPGAs can provide noteworthy benefits to enterprises.

Power requirements are very critical in modern networking ASIC design.

Introduction SoC (System-on-Chip) Verification effort mainly includes three key phases:

Introduction Assertion-based verification (ABV) is a powerful verification approach that

1. SoC Level/Top Level view (Feature Extractions) During SoC design

To gain knowledge and learn new things on professional front

In the era of miniaturization in the Semiconductor industry, ASIC

2.5D and 3D are the best alternatives to transistor scaling in order to sustain Moore’s law. Read this blog to know how it helps in the Semiconductor industry.

Due to immense complexities in Analog Mixed Signal SoC’s/chips, there

1. What is physical design? In VLSI, physical design (is

1. What is ASIC Design (Application Specific Integrated Circuit) in

Preventing Memory Overwrite Problem for Shared Memory using Exclusive Access of AMBA AXI

Reducing the Elaboration time in Silicon Verification with Multi-Snapshot Incremental Elaboration (MSIE)

What it means to be an ARM Approved Design Partner

Top 10 Contributing Factors to Design-for-Manufacturability (DFM)

Adopting the 64-bit ARM Architecture