Power requirements are very critical in modern networking ASIC design. Robust power planning often undergoes various limitations to tackle the limits of certain numbers. In this article, we have explained how advanced techniques like MBIT flops and MIMCAPs can help improve power and area numbers. By replacing and merging single bit flops with multibit flip-flops using different algorithms, we have significantly reduced area and power numbers for ASIC (FPGA) designs. On chip MIMCAP (Metal Insulator Metal capacitor) has reduced voltage fluctuation and noise on the power supply which may have affected signal integrity, reliability and speed of design.
Multibit flops are used to optimize switching power generally in clock networks and also for improving area numbers. A group of 2 register bits can be implemented as a single 2-bit library register. Using following method, we have converted major single bit flops in multiple blocks to 2-bit MBITS to achieve significant improvements.
Clock, set and reset condition must be the same for single bit flop and 2-bit flop. For Scan enabled flops, we have to use one scan input and one scan output for each register bit. Single scan-in and scan-out is also possible using some additional logic inside multibit flops. Both types of MBIT scan register architectures are supported.
There are multiple ways to convert single bit flops to multibit flops. We have found the following method efficient for our Networking ASICs.
Benefits of Multibit flops:
Disadvantages of Multibit flops:
|Dynamic Power Improvement after MBIT on
|50 Macros, 0.8M logic
|40% Reduction in clock network
|150 Macros, 1.5M logic
|35% reduction in clock network
|100 Macros, 1M logic
Table 1: comparison table of some blocks taken from networking ASIC.
We have 10% blocks like Case 3 where MBIT on is having broken results of timing and DRC. Those 10% blocks are with MBIT off. Another 90% blocks have MBIT on and with conversion ratio of 90-95% to multibit flops, Blocks are closed for signoff with all checks passed.
Overall ASIC Power Improvement:
What is MIMCAP?
Metal-Insulator-Metal (MIM) capacitors are parallel plate capacitors formed by two metal films. There is a thin insulating dielectric layer between Capacitor top metal- CTM and capacitor bottom metal- CBM layers. These MIM layers are made from Al, AlCu alloys, TiN, Ti, TaN, and Ta. While dielectric layers are made from silicon nitride or silicon oxide.
Why MIMCAP is needed?
The geometry scaling has led to thinner interconnects and reduced metal width. Interconnect lengths were also increased along with switching at gigahertz speeds to meet complex ASIC design requirement. The device scaling has increased the density of integrated transistors on the semiconductor wafer (Silicon). There may be large current spikes due to simultaneous switching within short periods of time, which can cause the current resistance drop, voltage fluctuation and noise on the power supply network. These will affect reliability, speed and signal integrity. The addition of on-chip decoupling MIMCAP compensate voltage fluctuations by supplying charges to the power network. However, the capacitance must be large enough to meet the requirement.
In 16nm project, the MIMCAP was placed between Metal 12 and Metal 11. A Metal-Insulator-Metal Capacitor (MIMCAP) uses a cut layer (V11) that connects a metal layer M12 to metal layer M11. The cut layer (V11) connects top layer metal layer M12 to intermediate layers CBM and CTM. The intermediate layers (CBM and CTM) are defined in the technology file with the MIMCAP function.
Table 2: Layer Function table for MIMCAP from Foundry.
Above figure shows 4X4 MIMCAP of size 46×55 um^2.The cell cap is 42pF and Cap Density = 42700fF / (46.08*55.296 um^2) = 16.8 fF/um^2.
It is a cover cell. It has via11 obstruction in MIM region and M11 obstruction under MIM vias. It has no CTM/CBM shapes. Coupling to CTM/CBM seen only in extraction.
MIMCAP cells are added to the blocks after power grid insertion. Decap cells are still required. MIMCAP doesn’t replace decaps, it rather adds to it. It is recommended to add these to places where there is little or no metal11 routing, since coupling to metal11 won’t be seen until extraction. It is recommended adding over high current density areas, such as TCAMs, high density or frequency logic areas, etc. There are placement rules regarding MIMCAP and die edge. Recommend >400u away from die edge.
In our 16nm networking chip of 22*15 mm size with mentioned usage of MBIT flops and MIMCAPs, we got significant clock/data dynamic power improvements and extra 750pF decap with cost of extra manufacturing mask layer.