Efficiently estimate & optimize leakage in SoCs

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Efficiently estimate & optimize leakage in SoCs

Description

As technology nodes shrink, the supply voltages of CMOS circuits are scaled down too, and because of that, standby leakage current increases, becoming significant. Until recent years, area and performance were the two main factors in the semiconductor industry. Now, leakage power has gained in importance. To reduce this, several leakage power minimization techniques have been proposed. These techniques are divided into two main categories: CAD-driven techniques, and technology-driven techniques. CAD-driven techniques use different kinds of circuit styles and design methodologies to minimize power. Technology driven techniques, like Silicon-On-Insulator (SOI), also minimize leakage power dissipation. This paper covers a CAD-driven technique, Multi-VT.

Publications

Introduction

As the technology is shrinking and density is increasing to millions of gates in single SoC, power dissipation in the chip due to leakage is becoming significant. The power has mainly two components: Dynamic Power and Static Power.

The static Power means power dissipation of cell when there is no input transition while dynamic power means Power dissipation of cell when the is input transition of cell. Static Power dissipation mainly happens due to sub-threshold current. In more recent times leakage power is big concern. The leakage power increases exponentially as threshold voltage is reduced.

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    Description

    As technology nodes shrink, the supply voltages of CMOS circuits are scaled down too, and because of that, standby leakage current increases, becoming significant. Until recent years, area and performance were the two main factors in the semiconductor industry. Now, leakage power has gained in importance. To reduce this, several leakage power minimization techniques have been proposed. These techniques are divided into two main categories: CAD-driven techniques, and technology-driven techniques. CAD-driven techniques use different kinds of circuit styles and design methodologies to minimize power. Technology driven techniques, like Silicon-On-Insulator (SOI), also minimize leakage power dissipation. This paper covers a CAD-driven technique, Multi-VT.

    Introduction

    As the technology is shrinking and density is increasing to millions of gates in single SoC, power dissipation in the chip due to leakage is becoming significant. The power has mainly two components: Dynamic Power and Static Power.

    The static Power means power dissipation of cell when there is no input transition while dynamic power means Power dissipation of cell when the is input transition of cell. Static Power dissipation mainly happens due to sub-threshold current. In more recent times leakage power is big concern. The leakage power increases exponentially as threshold voltage is reduced.

    Publications

    To read more, download the copy

    arrows-new-1

    To download this resource

    Fill in the details below






      I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

      I wish to be contacted by eInfochips I wish to be contacted by eInfochips

      For all career related inquiries, kindly visit our careers page or write to career@einfochips.com

      Fill in the details below






        I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

        I wish to be contacted by eInfochips I wish to be contacted by eInfochips

        For all career related inquiries, kindly visit our careers page or write to career@einfochips.com