DFT Challenges for Phase-Shifted Functional Clocks

In mixed-signal processing, design engineers use phase-shifted circuits, which lead to many challenges in DFT. Here are the common challenges of phase-shifted clock designs and ways to fix these challenges.

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ABOUT THE AUTHOR

Shalin Mandiwala

Shalin Mandiwala is working as an ASIC DFT Engineer at eInfochips, an Arrow company. He has more than three years of experience in ASIC DFT. He has an experience of working on various technology node, from 180nm to 7nm, handling different DFT tasks.