System Verilog Assertions Simplified

Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects.

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Smit Patel

Smit Patel is working as an Engineer at eInfochips, an Arrow company. He has an experience of almost 3 years in ASIC Design Verification and has worked on ATE domain verification projects. He also has a hands-on experience in Functional and SVA-based verification.