Implementation Challenges for Large 28nm SoCs

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ABOUT THE AUTHOR

Nilesh Ranpura

With 14+ years of experience in VLSI Design Cycle, Methodologies, Project execution and ODC set up Nilesh has participated in multiple projects for Verification, Physical design, DFT in the area of bus interface and Networking domain for Multi-million gate count SoC. His specialization is on ASIC product development and ODC growth solutions.

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