In the past, during the desktop PC era, VLSI design’s primary goal was to optimize the speed of the real-time computational functions such as gaming, video compressing, and graphics. Due to that, we now have semiconductor ICs that can integrate various graphical processing units and signal processing modules that have the ability to fulfill our demands for entertainment and computation. While these design efforts have achieved the real-time computation power, they have not addressed the increasing need of portable devices such as mobile phones that are capable enough to carry the same complex operations without consuming as much power.
The rising demand for portable and even wearable electronic devices for communication, computing, and entertainment has necessitated longer battery life, lower power consumption, and lesser device weight. Considering this, there seems a need to develop a solution that can make use of low voltage and low power design techniques. Now that power consumption is also considered as an important criterion in VLSI design, the design space might get expanded, thus adding to the complexity of the already significant tasks. In order to create an ideal solution for this problem, ‘low power design’ has to be considered as a crucial factor.
Power Dissipation in VLSI
Today’s consumers want a device that is packed with all the state-of-the-art features at a reasonably low price. They need mobile devices and applications that deliver the same level of efficiency as their non-mobile counterparts, without compromising the battery life. If we analyze the top features that consumers ask for in a smartphone, about 70% of users want a long talk and standby time. They want sleeker mobile phones, which might require high levels of silicon integration used for advanced processes; however, these processes have higher power dissipation, which further results in increased temperature.
Power dissipation can be defined as the product of total current supplied to the circuit and the total voltage loss or leakage current. When it comes to portability of devices, power dissipation is an unavoidable constraint.
Why does Power Consumption matter so much in SoCs?
Power management is important in System on Chip because of the following reasons:
- Costs associated with packaging and cooling
- Standby time and battery life
- Digital noise immunity
- Environmental concerns
Types of Power Dissipation
In the circuits, power dissipation can be categorized into the following types:
Static power dissipation: The power dissipation occurs in the form of leakage current when the system is not powered or is in standby mode. In circuits, there are several sources of leakage current including subthreshold leakage, diode leakages around transistors and n-wells, tunnel currents, gate leakage, etc.
Dynamic power dissipation: Logic transitions cause logic gates to charge and discharge load capacitance. In other words, this type of power dissipation occurs due to switching activities of transistors.
Minimizing Power Dissipation with Low Power Design
Several measures can be taken by VLSI companies to reduce the power dissipation. Some of the ways in which low power design can be implemented are discussed below:
Reduce supply voltage
Reducing voltage can prove to be an effective way to reduce power consumption. Without needing any special technologies or circuits, a factor of two reductions in the supply voltage can result in a factor of four reductions in the power consumption. However, the performance is also reduced by reducing the supply voltage, which can be avoided by scaling down the threshold voltage.
Physical capacitance
The dynamic power consumption of the circuit directly depends on the physical capacitance being switched. So, over and above reducing voltage, reducing capacitance can be another way to achieve lower dissipation.
Design process
Low power VLSI can be achieved by optimization at numerous levels of the design process starting from the system and algorithmic levels to circuit and layout levels.
System level
Partitioning and power down
Algorithm level
Complexity, regularity, and concurrency
Architecture level
Parallelism, redundancy, pipelining, and data encoding
Circuit level (logic)
Energy recovery, logic styles, and transistor sizing
Technology level
Threshold reduction and multi-threshold devices
Wrapping Up
With a growing number of handheld devices, every one of us wants to own a device that is powerful, compact, and power efficient. This is the reason why chip designers are moving to low geometry design, working on smaller and smarter chips.
Over the time, eInfochips has delivered RTL to GDSII service to many of its clients for successful Silicon tapeouts. We were the first engineering services company to tapeout multiple 16nm System on Chips and now we are working on 10nm and 7nm technology nodes. These SoCs are packed with 300 million to 500 million gates (~25*25 mm) and are developed with a focus on reducing power consumption. If you wish to get your hands on these low geometry chip designs, get in touch with us.
