Learn about the antenna effect observed in the 16nm technology node and the way to identify antenna violations in chip design using different PV tool. It also described three different methods to fix the violations.
Effect of charge accumulation in isolated nodes of an integrated circuit during its processing is known as Antenna effect. This effect is also known as Plasma Induced Damage. The discharging of accumulated charges, which is done through the thin gate oxide of the transistor, it might cause damage to the chip and degrade its performance. During the fabrication process, we need to etch out the unwanted oxide layer from the wafer, which can be done using plasma etching. Plasma contains high energetic ions and radicals for etching that get collected by interconnect. The amount of charge accumulation depends on the surface area of interconnects. These collected ions increase the potential of interconnects and if the interconnect is connected to gate, a drainage path could be formed through the gate oxide to balance out the charge collection depending upon the amount of charge collected by interconnects. The drainage path could either breakdown the gate oxide, which may lead to permanent damage of the device. During the plasma etching of interconnect, positive ions and neutral species from the plasma get strikes at interconnector these are collected by the interconnects, so if the area of the interconnect connected to the gates is large enough then the potential of the interconnect or poly silicon maybe large enough that it could breakdown the gate oxide.
Etching refers to the removal of material from the wafer surface. There are two main types of etching:
In this process, chemical etchant is introduced in the gas phase. For etching silicon oxide, CF4 (tetrafluoromethane) is used. In a chamber, there are two electrodes; one is holding a wafer and a very high electric field created between these two electrodes. The chamber is first evacuated before introducing the gas. Radio frequency electrodes are then used to generate the plasma that ionizes the gas. This ionized gas attacks the oxide layer and remove the layer.
When high energetic ions beam are bombarded on the target that dislodge portion of the material from the exposed surface.
Violations to the above antenna rules in every metal layer have to be fixed before the chip tape out. Fig 3 shows the design layout of one piece of metal connected to a poly gate. The poly gate with L and W for gate length and gate width and gate area is W*L. The perimeter antenna ratio for figure is defined as follows:
R=(P*T)/(W*L)
In fig 3, P is the sum of the periphery length for the metal as shown in figure. T is the thickness of the metal. W and L are the gate width and gate length. The perimeter antenna rule specifies the upper limit for R. If we increase the W or L for gate or decrease P for metal line, the ratio R is reduced. Each metal layer may have various upper limit to R based on the process specifications.
Techniques to fix the antenna violations as follows:
Chip is on 16 nm technology which is being operated at 1GHZ and its size is 7900.0 x 3244.0
We faced Some Antenna violations while working on it.
via89_1cut
via area: 0.219
Via67_Long_H
via area: 0.0168
7. Conclusion:
In this blog, author discussed about the antenna effect due to plasma etching and different PV tools used to identify antenna effect by comparing design GDS and antenna rule file provided by foundry. And by adding diode, routing to upper metal layer and reducing via area, can solve the antenna violation.
Tool Used: IC Validator, ICC2
REFERENCE
[1] Peter H. Chen and Sunil Malkani, Chun-MouPeng, James Lin, Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion.
[2] Jean-Pierre Carrère, Jean-Claude Oberlin, Sylvie Bruyère, Paul Ferreira plasma damage in ultra-thin gate oxide induced by dielectric deposition processes: An overview on main mechanisms and characterization technique.
Upma Pawan Kumar & Sunandan Choubey
