With a proven physical design flow, methodologies, and with dedicated subject matter experts, eInfochips have helped many clients with successful Silicon tapeouts. We are the 1st engineering services company to tapeout multiple 16nm SoC’s. These SoC’s have 300 million to 500 million gates (~25*25 mm) and was developed with the focus on reducing the die size and power. We have recently started working on 10nm as well. We have delivered multiple tapeouts to leading foundries including TSMC, UMC, GF, Toshiba, TI and SMIC.
eInfochips also offers DFT services, including architecture definition and implementation, pre silicon validation, post silicon validation and yield analysis. We have enabled 200+ tapeouts and silicon turn-on across 130nm to 16nm with 99% of coverage.
Complete Turnkey Ownership: 100+ Silicon Tape-outs across 180 to 16nm
First engineering services company to tapeout multiple 16nm SoC’s with:
-300 to 500 million gates
-Large die size (~25*25 mm)
-200 Watts Power consumption
Flexible DFT engagement model starting from DFT Architecture to Silicon Turn-on
40+ successful ASIC/SoC DFT silicon bringup
1. What is physical design?
In VLSI, physical design (is also known as integrated circuit layout) is a process in which the front end design transfer the structural netlist to the back end design team to convert into a physical layout database which consists of geometrical design information for all the physical layers which is used for interconnections.