DFT, DFM & Physical Design Services | Silicon Turnkey Solutions

Lower Geometry Specialists

With a proven physical design flow (RTL to GDSII, DFT, DFM), methodologies, and with dedicated subject matter experts, eInfochips has provided silicon turnkey design service to many clients for successful silicon tape-outs. We were the 1st engineering services company to tape-out multiple 16nm SoCs and at present, we are working on 10nm and 7nm ASIC technology node. These SoCs have 300 million to 500 million gates (~25*25 mm) and were developed with the focus on reducing the die size and power.

We have recently started working on 5nm as well. We have delivered multiple tape-outs to leading foundries including TSMC, UMC, GF, Toshiba, TI, and SMIC. We also offer DFM (Design for manufacturability)/DFT (Design for testing) and silicon turnkey design services for startups and tier-2 companies.

Why eInfochips for Specification to Silicon Services?

Silicon Tape-outs across 180 to 16nm

Complete Silicon Turnkey Solutions Ownership: 100+ Silicon Tape-outs across 180 to 16nm

First engineering services company to tapeout multiple 16nm

First engineering services company to tapeout multiple 16nm SoC’s with:

-300 to 500 million gates
-Large die size (~25*25 mm)
-200 Watts Power consumption

DFT Services - Architecture to Silicon Turn-on

Flexible DFT engagement model starting from DFT Architecture to Silicon Turn-on

ASIC/SoC physical design

40+ successful ASIC/SoC DFT-DFM silicon bringup

Design Layout & RTL to GDSII Services

  • RTL Synthesis, Physical Synthesis
  • DFM/DFT testing, ATPG & fault grading services
  • Hierarchical floor planning & partitioning
  • Place & Route, Customized Clock Tree Synthesis, Signal Integrity Analysis
  • Signoff Services – Power/EM/IR/Noise, STA with On-Chip Variation (OCV), Physical Verification
  • Structural, Ad-hoc DFT strategy
  • DFT architecture – SCAN, MBIST, LBIST, ATPG Flat/Hierarchical Partition, Boundary Scan
  • Test program development – Advance fault model implementation and design validation, program quality improvement and checklist
  • Wafer level Reliability Testing, Die and Package level testing support
  • Silicon turnkey bring up support, Yield analysis and improvement

Q&A on Physical Design And Verification Methodologies

1. What is the need of design for testability (DFT) in VLSI?

The two major reasons behind the need for DFT in VLSI is productivity and quality. Productivity includes:
Faster and right time to market, Reduced design check rules and cycles, Reduced design cost. Quality includes: Reduced defects per million (DPM), Improved quality testing and operation

2. What is DRC?

DRC is a process where the entire physical design database is checked against design rules. The design layout must adhere to the standards defined by the foundry for manufacturability. DRC was introduced as the lower geometry design technology has evolved vigorously. Understand how design rule checks are applied for 28nm node technology: https://goo.gl/afrNKd

FAQ's in DevOps

Customer Success Stories

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