As technologies advance, we see increasingly complex SoCs in the market, SoCs that have various
wireless modules, and processors that use new bus architectures to communicate with them. They can also have various interfaces like I2C, PCM, I2S, AHB, etc. Yet, these SoC components will share a single clock control unit. This module generates the various clock inputs for IPs and protocols, enabling them to function seamlessly. Each module may require a different clock frequency based on the divider settings, which can be programmed through registers. Often, some IPs and protocols will require changes to the clock frequency on the fly. For verification, one should test all possible combinations of clock frequencies that their control unit supports, and check that the modules operate without a glitch. This can easily be verified by what is called a clock monitor. This paper presents the concept of a reusable clock monitor that can verify complex clock systems.

The semiconductor industry is in a constant race to be first-to-market with the significant first move advantage. This puts pressure on the verification process, to shrink overall development time. In SoCs, the clock control unit is critical, and this is not a standard IP. A clock monitor is a SV/UVM based component to monitor the clock under test. As the functionality of clock monitor is unique and flexible, and can we re-use it on different types of SoCs.