Analog Modeling and Validation of DDR4 Memory IP
Executive Summary
The client designs, manufactures, and markets low-power, high-performance mixed-signal semiconductor solutions for advanced communications, computing, and consumer industries. The client’s portfolio includes market-leading products in RF, high-performance timing, memory interface, real-time interconnect, optical interconnect, wireless power, and smart sensors. The client’s IDT’s DDR4 IP portfolio makes up the industry’s first complete chipset for DDR4 registered dual inline memory modules (RDIMMs) and load reduced dual inline memory modules (LRDIMMs) that are expected to be adopted for a broad array of memory-intensive computing and storage applications.
The client was looking for a partner who can provide a comprehensive and efficient verification solution for their memory IPs. eInfochips proposed SV-RNM (System Verilog Real Number Modeling) model-based verification approach to support multiple memory configurations.
Project Highlights
- SV – Real Number Modeling
- Customized Model Validation Flow
- DDR4 JEDEC Rev 1.0 Compliant
- Supports all LRDIMM Raw Card
- Developed 25 Models
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Executive Summary
The client designs, manufactures, and markets low-power, high-performance mixed-signal semiconductor solutions for advanced communications, computing, and consumer industries. The client’s portfolio includes market-leading products in RF, high-performance timing, memory interface, real-time interconnect, optical interconnect, wireless power, and smart sensors. The client’s IDT’s DDR4 IP portfolio makes up the industry’s first complete chipset for DDR4 registered dual inline memory modules (RDIMMs) and load reduced dual inline memory modules (LRDIMMs) that are expected to be adopted for a broad array of memory-intensive computing and storage applications.
The client was looking for a partner who can provide a comprehensive and efficient verification solution for their memory IPs. eInfochips proposed SV-RNM (System Verilog Real Number Modeling) model-based verification approach to support multiple memory configurations.
Project Highlights
- SV – Real Number Modeling
- Customized Model Validation Flow
- DDR4 JEDEC Rev 1.0 Compliant
- Supports all LRDIMM Raw Card
- Developed 25 Models
To download this resource
Fill in the details below
Executive Summary
The client designs, manufactures, and markets low-power, high-performance mixed-signal semiconductor solutions for advanced communications, computing, and consumer industries. The client’s portfolio includes market-leading products in RF, high-performance timing, memory interface, real-time interconnect, optical interconnect, wireless power, and smart sensors. The client’s IDT’s DDR4 IP portfolio makes up the industry’s first complete chipset for DDR4 registered dual inline memory modules (RDIMMs) and load reduced dual inline memory modules (LRDIMMs) that are expected to be adopted for a broad array of memory-intensive computing and storage applications.
The client was looking for a partner who can provide a comprehensive and efficient verification solution for their memory IPs. eInfochips proposed SV-RNM (System Verilog Real Number Modeling) model-based verification approach to support multiple memory configurations.
Project Highlights
- SV – Real Number Modeling
- Customized Model Validation Flow
- DDR4 JEDEC Rev 1.0 Compliant
- Supports all LRDIMM Raw Card
- Developed 25 Models
To download this resource
Fill in the details below