Verification & Physical Design of Optical Ethernet ASIC

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Verification & Physical Design of Optical Ethernet ASIC

Executive Summary

Hyperscalers are continuing to expand their network capacity to meet the growing bandwidth demands. All the information collection, analysis, and content trasfer results in increased internal data traffic. In order to support the growing internal data traffic,  they need to evolve their internal network infrastructure, which is also an area of focus. The interconnects that make up the data center network infrastructure, play an important role in a hyperscaler’s network evolution.

The client planned to introduce 400G switches and pluggable optical modules that can enable hyperscalers to transform how data center networks are being architected, with an anticipated impact of comparable magnitude to when 10G and later 100G solutions will be introduced. These 400G solutions are designed to enable network operators to address increasing bandwidth demands through  simplified network architecture, targeting the reduction of both CapEx and OpEx. They were looking for an engineering partner who has strong expertise in the networking domain and 7nm technology node.

Project Highlights

  • Mapping X100GBASER & 400GBASER Ethernet stream in OTN/OTU4 Frame
  • Targeted for Data Center interconnect, metro, long-haul
  • Chip Size : 4mmx3mm
  • Technology Node: 7nm
  • Core frequency : 500Mhz

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    Executive Summary

    Hyperscalers are continuing to expand their network capacity to meet the growing bandwidth demands. All the information collection, analysis, and content trasfer results in increased internal data traffic. In order to support the growing internal data traffic,  they need to evolve their internal network infrastructure, which is also an area of focus. The interconnects that make up the data center network infrastructure, play an important role in a hyperscaler’s network evolution.

    The client planned to introduce 400G switches and pluggable optical modules that can enable hyperscalers to transform how data center networks are being architected, with an anticipated impact of comparable magnitude to when 10G and later 100G solutions will be introduced. These 400G solutions are designed to enable network operators to address increasing bandwidth demands through  simplified network architecture, targeting the reduction of both CapEx and OpEx. They were looking for an engineering partner who has strong expertise in the networking domain and 7nm technology node.

    Project Highlights

    • Mapping X100GBASER & 400GBASER Ethernet stream in OTN/OTU4 Frame
    • Targeted for Data Center interconnect, metro, long-haul
    • Chip Size : 4mmx3mm
    • Technology Node: 7nm
    • Core frequency : 500Mhz

    To read more, download the copy

    arrows-new-1

    To download this resource

    Fill in the details below






      I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

      I wish to be contacted by eInfochips I wish to be contacted by eInfochips

      For all career related inquiries, kindly visit our careers page or write to career@einfochips.com

      Executive Summary

      Hyperscalers are continuing to expand their network capacity to meet the growing bandwidth demands. All the information collection, analysis, and content trasfer results in increased internal data traffic. In order to support the growing internal data traffic,  they need to evolve their internal network infrastructure, which is also an area of focus. The interconnects that make up the data center network infrastructure, play an important role in a hyperscaler’s network evolution.

      The client planned to introduce 400G switches and pluggable optical modules that can enable hyperscalers to transform how data center networks are being architected, with an anticipated impact of comparable magnitude to when 10G and later 100G solutions will be introduced. These 400G solutions are designed to enable network operators to address increasing bandwidth demands through  simplified network architecture, targeting the reduction of both CapEx and OpEx. They were looking for an engineering partner who has strong expertise in the networking domain and 7nm technology node.

      Project Highlights

      • Mapping X100GBASER & 400GBASER Ethernet stream in OTN/OTU4 Frame
      • Targeted for Data Center interconnect, metro, long-haul
      • Chip Size : 4mmx3mm
      • Technology Node: 7nm
      • Core frequency : 500Mhz

      To read more, download the copy

      arrows-new-1

      To download this resource

      Fill in the details below






        I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

        I wish to be contacted by eInfochips I wish to be contacted by eInfochips

        For all career related inquiries, kindly visit our careers page or write to career@einfochips.com