Challenges of power optimization for high-speed designs


In the latest SOC (System-on-chip), the transistor count is increasing in modern VLSI designs to add new architecture features leading to more power dissipation in the design. Earlier area and performance were the two main factors of the semiconductor industry but in the latest technology nodes, the frequency of the design is enhancing. As the frequency rises, the power dissipation of the circuit escalates, subsequently causing an upsurge in leakage current. Consequently, this affects the chip’s cost, overall quality, and performance.

Hence, power reduction has become important, and some techniques are implemented on the low power designs to reduce the power dissipation on the chips. Power management is important in SOC because of the battery lifetime, environmental concerns, packaging costs, and noise immunity.

Project Highlights

  • Methods to Reduce Dynamic Power
  • Methods to Reduce Static Leakage Current
  • Variable Threshold CMOS
  • Power Optimization at Different Levels
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