Low Power Design – A Game Changer in ASIC Physical Design

Power reduction has been on the top priority list of chip designers. The question at hand is: are positioned to address this problem? Are we getting the best combination of power, performance, and area in our chips? Are the EDA tools that we are using equipped to do so? What steps can we take to resolve this challenge?

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ABOUT THE AUTHOR

Vipulkumar Patel

Vipulkumar is a senior Physical Design engineer with 7 years’ experience in Very Large Scale Integration/Application Specific Integrated Circuits field. He has worked on different nanometer technology nodes (16nm,28nm,40nm,65nm) of ASIC design Chips (SoC) in the semiconductor industry from RTL netlist to GDS II, Sign off process. He is experienced in Place & Route, Static Timing Analysis, and Layout Verification, Signal Integrity analysis, and Low power technique implementation.