Sign Off the Chip (ASIC) Design Challenges and Solutions at Cutting Edge Technology

Today’s cutting-edge technology has introduced a lot of challenges with new strategies and techniques for lower node technology i.e. 16nm, 7nm, 5nm, and below. These challenges are double patterning, FinFET statistical analysis, PDV closure, and optimization capabilities to achieve better Power-Performance-Area (PPA) on vigorous project timelines. The key milestone in developing ASIC is taping it out on right time. In this blog, we will discuss several challenges and solutions that can be used to signoff the design like: Timing closure, pdv closure techniques, RPCT, and packaging complexity.

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Ruchita Shah

Ruchita Shah is a Physical Design Engineer at eInfochips, where she works on different technology nodes including 28nm, 16nm, and 7nm. She holds a gold medal in M.Tech; she has completed her M.Tech in VLSI & Embedded Systems from U.V. Patel College of Engineering, Ganpat University. In her free time, she loves crafting and gardening.

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