Physical Design of a 7nm based Superfast Programmable Ethernet Switch ASIC
Executive Summary
Today, internet networks have grown exponentially, at a rate that was unimaginable a few years ago. With increasing requirements of cloud computing, sophisticated network connections, proliferation of artificial intelligence and machine learning technology, and overall global adoption of distributed applications, the demand for improved reliability, visibility, security, AI and ML workloads, and storage across networking architectures has also increased. To address this demand, our client, a US-based startup, has built a fully programmable networking ASIC using Protocol Independent Switch Architecture (PISA).
The client was planning to design a second generation chip, with full programmability above 10 Tbps packet processing speed. Based on 7nm technology node, the chip aimed to deliver double the performance compared to its first generation chip, making it an ideal choice for cloud, hyperscale data centers and service provider networks. To accomplish this ambitious goal, the client was looking for an engineering partner with expertise in physical layout of chips at 7nm technology.
Project Highlights
- World’s first programmable chip
- Size >500mm2 and frequency >1GHz
- Targeted for Hyperscale data centers
- Processing above 10 TBPS
- RTL to GDSII at 7nm Technology node
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Executive Summary
Today, internet networks have grown exponentially, at a rate that was unimaginable a few years ago. With increasing requirements of cloud computing, sophisticated network connections, proliferation of artificial intelligence and machine learning technology, and overall global adoption of distributed applications, the demand for improved reliability, visibility, security, AI and ML workloads, and storage across networking architectures has also increased. To address this demand, our client, a US-based startup, has built a fully programmable networking ASIC using Protocol Independent Switch Architecture (PISA).
The client was planning to design a second generation chip, with full programmability above 10 Tbps packet processing speed. Based on 7nm technology node, the chip aimed to deliver double the performance compared to its first generation chip, making it an ideal choice for cloud, hyperscale data centers and service provider networks. To accomplish this ambitious goal, the client was looking for an engineering partner with expertise in physical layout of chips at 7nm technology.
Project Highlights
- World’s first programmable chip
- Size >500mm2 and frequency >1GHz
- Targeted for Hyperscale data centers
- Processing above 10 TBPS
- RTL to GDSII at 7nm Technology node
To download this resource
Fill in the details below
Executive Summary
Today, internet networks have grown exponentially, at a rate that was unimaginable a few years ago. With increasing requirements of cloud computing, sophisticated network connections, proliferation of artificial intelligence and machine learning technology, and overall global adoption of distributed applications, the demand for improved reliability, visibility, security, AI and ML workloads, and storage across networking architectures has also increased. To address this demand, our client, a US-based startup, has built a fully programmable networking ASIC using Protocol Independent Switch Architecture (PISA).
The client was planning to design a second generation chip, with full programmability above 10 Tbps packet processing speed. Based on 7nm technology node, the chip aimed to deliver double the performance compared to its first generation chip, making it an ideal choice for cloud, hyperscale data centers and service provider networks. To accomplish this ambitious goal, the client was looking for an engineering partner with expertise in physical layout of chips at 7nm technology.
Project Highlights
- World’s first programmable chip
- Size >500mm2 and frequency >1GHz
- Targeted for Hyperscale data centers
- Processing above 10 TBPS
- RTL to GDSII at 7nm Technology node
To download this resource
Fill in the details below