Design for Testability for a High-speed Gigabit Ethernet Controller for Networking

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Design for Testability for a High-speed Gigabit Ethernet Controller for Networking

Executive Summary

The client is a pioneer in providing solutions for server connectivity of Neural Class Networks. Right from silicon to firmware to software, they specialize in delivering a comprehensive and integrated set of technologies for distributed, ultra-scale, software-defined data centers. The client was looking for a team of ASIC design experts who can help them in integrating Design for Testability (DFT) for Gigabit Ethernet Controller, a complex ASIC at 28nm technology node to enable high-performance and multi-terabyte throughput.

eInfochips, being an expert ASIC design and DFT solution provider, helped the client successfully tape out 28nm ASIC design for their Ethernet Controller. This helped the client to expand the capability of Software Defined NICs for the applications at run time to leverage one or more different NIC firmware modules.

Project Highlights

  • 28nm Node for TSMC tape-out
  • High Performance with 40G Switch Throughput
  • 50mm2 die size with High-end Networking
  • ~2.74 Million Gates/mm2

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Executive Summary

The client is a pioneer in providing solutions for server connectivity of Neural Class Networks. Right from silicon to firmware to software, they specialize in delivering a comprehensive and integrated set of technologies for distributed, ultra-scale, software-defined data centers. The client was looking for a team of ASIC design experts who can help them in integrating Design for Testability (DFT) for Gigabit Ethernet Controller, a complex ASIC at 28nm technology node to enable high-performance and multi-terabyte throughput.

eInfochips, being an expert ASIC design and DFT solution provider, helped the client successfully tape out 28nm ASIC design for their Ethernet Controller. This helped the client to expand the capability of Software Defined NICs for the applications at run time to leverage one or more different NIC firmware modules.

Project Highlights

  • 28nm Node for TSMC tape-out
  • High Performance with 40G Switch Throughput
  • 50mm2 die size with High-end Networking
  • ~2.74 Million Gates/mm2

To read more, download the copy

arrows-new-1

To download this resource

Fill in the details below





I wish to be contacted by eInfochips

Executive Summary

The client is a pioneer in providing solutions for server connectivity of Neural Class Networks. Right from silicon to firmware to software, they specialize in delivering a comprehensive and integrated set of technologies for distributed, ultra-scale, software-defined data centers. The client was looking for a team of ASIC design experts who can help them in integrating Design for Testability (DFT) for Gigabit Ethernet Controller, a complex ASIC at 28nm technology node to enable high-performance and multi-terabyte throughput.

eInfochips, being an expert ASIC design and DFT solution provider, helped the client successfully tape out 28nm ASIC design for their Ethernet Controller. This helped the client to expand the capability of Software Defined NICs for the applications at run time to leverage one or more different NIC firmware modules.

Project Highlights

  • 28nm Node for TSMC tape-out
  • High Performance with 40G Switch Throughput
  • 50mm2 die size with High-end Networking
  • ~2.74 Million Gates/mm2

To read more, download the copy

arrows-new-1

To download this resource

Fill in the details below





I wish to be contacted by eInfochips