Physical Design of Data Center ASIC

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Physical Design of Data Center ASIC

Executive Summary

The client, a niche data center infrastructure start-up, is working on an innovative product that will revolutionize data centers in terms of their security, reliability and economics. They plan to launch a niche ASIC that combines custom silicon with integrated compute, storage, and networking.

This high throughput ASIC was quite complex and included a number of complex interfaces and IPs. For this product, targeted for 16nm technology node, the client was looking for a partner capable of helping in ASIC layout, with a strong focus on die size optimization and performance.

eInfochips , having taped out multiple 16nm networking ASICs, has a strong experience on lower geometries. eInfochips took the complete ownership of the physical design of the client’s ASIC (Netlist to GDSII) and was able to  meet the stringent technical and timeline requirements.

Project Highlights

  • High throughput, programmability
  • Netlist to GDSII at 16nm
  • 400Mn gates, 50+ unique blocks
  • Complex IPs: HBM, Ethernet, 100Gbps, SerDesPHY

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Executive Summary

The client, a niche data center infrastructure start-up, is working on an innovative product that will revolutionize data centers in terms of their security, reliability and economics. They plan to launch a niche ASIC that combines custom silicon with integrated compute, storage, and networking.

This high throughput ASIC was quite complex and included a number of complex interfaces and IPs. For this product, targeted for 16nm technology node, the client was looking for a partner capable of helping in ASIC layout, with a strong focus on die size optimization and performance.

eInfochips , having taped out multiple 16nm networking ASICs, has a strong experience on lower geometries. eInfochips took the complete ownership of the physical design of the client’s ASIC (Netlist to GDSII) and was able to  meet the stringent technical and timeline requirements.

Project Highlights

  • High throughput, programmability
  • Netlist to GDSII at 16nm
  • 400Mn gates, 50+ unique blocks
  • Complex IPs: HBM, Ethernet, 100Gbps, SerDesPHY

To read more, download the copy

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To download this resource

Fill in the details below





I wish to be contacted by eInfochips

Executive Summary

The client, a niche data center infrastructure start-up, is working on an innovative product that will revolutionize data centers in terms of their security, reliability and economics. They plan to launch a niche ASIC that combines custom silicon with integrated compute, storage, and networking.

This high throughput ASIC was quite complex and included a number of complex interfaces and IPs. For this product, targeted for 16nm technology node, the client was looking for a partner capable of helping in ASIC layout, with a strong focus on die size optimization and performance.

eInfochips , having taped out multiple 16nm networking ASICs, has a strong experience on lower geometries. eInfochips took the complete ownership of the physical design of the client’s ASIC (Netlist to GDSII) and was able to  meet the stringent technical and timeline requirements.

Project Highlights

  • High throughput, programmability
  • Netlist to GDSII at 16nm
  • 400Mn gates, 50+ unique blocks
  • Complex IPs: HBM, Ethernet, 100Gbps, SerDesPHY

To read more, download the copy

arrows-new-1

To download this resource

Fill in the details below





I wish to be contacted by eInfochips