With a proven physical design services and flow (RTL to GDSII, DFT, DFM), methodologies, and with dedicated subject matter experts, eInfochips has provided silicon turnkey design service to many clients for successful silicon tape-outs. We were the 1st engineering services company to tape-out multiple 16nm SoCs and have taped-out multiple ASICs at 7nm, 5nm and 3nm ASIC technology node. These SoCs have 300 million to 500 million gates (~25*25 mm) and were developed with the focus on power, performance and area requirements(PPA).
We have delivered multiple tape-outs to leading foundries including TSMC, UMC, GF, Toshiba, TI, and SMIC. We also offer DFM (Design for manufacturability)/DFT (Design for testing) and silicon turnkey design services for startups and tier-2 companies.
400+ across 180nm to 3nm technology node
First engineering services company to tapeout multiple 16nm SoC’s with:
-300 to 500 million gates
-Large die size (~25*25 mm)
-200 Watts Power consumption
Experience RISC-V core, IP integration and hardening
DFT Services – Architecture to Silicon Turn-on; Flexible DFT engagement model starting from DFT Architecture to Silicon Turn-on; 40+ successful ASIC/SoC DFT-DFM silicon bring-up
Best-in-the-world verification expertise
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