ASIC Design & Verification Services

First ASIC design services company to tape-out multiple 16nm SoC's. Leveraging our team of 400+ ASIC design and verification engineers, we have enabled 200+ tape-outs across 180 to 16nm technology nodes.

Client Speak

Appreciate eInfochips for their thoroughness in DO- 254 compliant development, which delighted our end customer

- Manager, Worldwide leader for aerospace and defense solutions.

ASIC / SoC / FPGA Services

ASIC SOC FPGA ServiceseInfochips is recognized as one of the top VLSI Engineering Services company by multiple analysts across the world. We work with 4 of the global Top-5 semiconductor companies, and are the first services company to tape-out 16nm silicon. Our team has experience of over 150 SoC tape-outs, in addition to multiple FPGA design and verification projects. We have worked on EDA tool chains from Cadence, Mentor Graphics, and Synopsys, and hands-on experience with FPGA devices from Microsemi, Altera and Xilinx.

Our VLSI processes and checklists have matured as we have executed complex projects in networking, consumer devices, automotive, smartphones, multimedia, aerospace, servers, automated test equipment, and MEMS. We have also contributed to Verification IPs (VIPs) that are used by thousands of engineers across the world.

Differentiators:

  • Expertise from spec-to-silicon (RTL-GDSII-DFT)
  • 200+ Tape-outs from 180 to 16nm technology nodes
  • First engineering services company to tapeout multiple 16nm SoC’s with:
    • 300 to 500 million gates
    • Large die size (~25*25 mm)
    • 200 Watts Power consumption
  • Expertise across verification disciplines: IP, Cluster, SoC, Formal, Low Power, Mixed signal, HW-SW co-simulation
  • Experience in high-speed interfaces and protocol standards:
    • NVMe, eMMC, DDR3/4, UFS, SONET NAND Flash, ONFI, SATA, LPDDRx Family
    • USB2.0, USB3.0/3.1, USB PD, 10/40/100G Ethernet, MIPI, SerDes, PCI-E Gen 1/2/3
    • FlexRay, CAN, ARINC-429, ARINC 429, ARINC 485, ARINC 664 (AFDX)
  • 50+ field proven Verification IPs
  • Found 100+ bugs in market proven design IPs

Our Service Offerings:

FPGA Design

  • Feasibility Study
  • Architecture Definition
  • Micro-architecture design
  • RTL Coding & Linting
  • Functional Verification
  • Synthesis and Optimization
  • Floor-planning & Timing Closure
  • ASIC Prototyping

ASIC RTL Design

  • Micro-architecture design
  • RTL Coding & Linting
  • Functional Verification
  • SoC integration
  • IP Development

Verification

  • SOC/IP Functional Verification
  • Low Power Verification
  • Analog Mixed Signal Verification
  • Hardware & Software Co-verification
  • VIP Development & Verification
  • SystemC /TLM Modelling
  • Formal Verification
  • EDA Tool Validation
  • Post-Silicon Bring up and Validation

Physical Design & DFT

  • RTL Synthesis, Physical Synthesis
  • DFT, ATPG & Fault grading services
  • Hierarchical Floor planning & Partitioning
  • Place & Route, Customized Clock Tree Synthesis, Signal Integrity Analysis
    • Signoff Services - Power/EM/IR/Noise, STA with On-Chip Variation (OCV),
    • Physical Verification
    • Layout migration
    • Custom Package design

With our stringent process checklists, we have identified 150+ defects from market proven Design and Verification IPs. Our team has experience on building modular, reusable verification environment

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Client Speak

Appreciate eInfochips for their thoroughness in DO- 254 compliant development, which delighted our end customer

- Manager, Worldwide leader for aerospace and defense solutions.