The VLSI design cycle is divided into two phases: Front-end and Back-end. Front-end covers the architectural specifications, coding and verification, whereas back-end involves the physical implementation of the design on the targeted technology node.

This paper presents why LEC (Logical Equivalence Check) is important in the ASIC design cycle, how to check it, and what to do when LEC is failing. We will explore a test case to see what happens if LEC fails – how to pinpoint the problem and what steps to take for resolving the same.