Low Power Networking ASIC

Executive Summary

This was one of the earliest design projects for 16nm geometry for the customer, a global data networking giant with revenues of about $5 Billion. Since 16nm geometry represents less than 1% of the chips on the planet, hence that design experience is rare to find. Also, a stringent timeline was to be adhered to for the delivery.

The plan was to deploy a combination of tools from various EDA vendors. The customer had a fixed date for tape-out and the entire schedule was worked backwards to align with it. The design had large block sizes, that led to congestion and STA complexity. The client was able to keep the engineering schedules on track to deliver the physical design and DFT as scheduled for meet their market commitments.

The customer delivered their first 16nm low-power chip for tape-out, on schedule.

Project Highlights

    • 16nm Geometry
    • 120+ Million Gates
    • ~85 Million Instances
    • 732 MHz Design
    • Tape-out with TSMC® ul>
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