Blogs - Semiconductor
Signoff Iteration Reduction Technique for Fixing Top Level Antenna
While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design,
Memory Testing: MBIST, BIRA & BISR | An Insight into Algorithms and Self Repair Mechanism
Typically, we see a 4X increase in memory size every 3 years to cater to
How to Deliver On-Time at Lower Technology Nodes (7nm,10nm,16nm…)?
Over the years, we have seen a wide range of advancements in semiconductor design services.
A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology
The intent of this paper is to explain the varied kinds of DRCs (Design Rule
Reducing DFT Footprints: A Case in Consumer SoC
Nowadays, placing multiple IPs on a single chip plays the most vital role in satisfying
Enhancing the Situational Awareness of Pilots with Voice Assistance
This article explores the role of voice messages for cockpit display systems in avionics. In
Low Power Design – A Game Changer in ASIC Physical Design
With the advent of personal computers and integrated circuits, the target has been to fit
DFT Cost Reduction and Improved TTR with Shared Scan-in DFTCODEC
With advanced technology nodes, the SoCs are growing in density and gate count. This creates
A Guide on Logical Equivalence Checking – Flow, Challenges, and Benefits
Introduction The VLSI design cycle is divided into two phases: Front-end and Back-end. Front-end covers