To keep up the pace with Moore’s law, manufacturing technology nodes keep decreasing so much

Coverage is traditionally used as a confidence-building metric and the quality of verification is measured based on it. Coverage works as a safety net to ensure that the design is verified thoroughly and keeps track of the progress of the verification process. While verifying a complex SoC (System on Chip) or IP (Intellectual Property), we invest most of our time in other verification phases like planning, development, and debugging. We generally struggle to close on coverage numbers. The purpose of this article is to highlight some hidden but useful coverage commands supported by the Cadence IMC tool that can help to ease and speed up the coverage closure.

Introduction Analog-centric and digital-centric simulations are two different types of mixed-signal simulations. The real challenges

Many organizations may have a great concept for a product or a solution or an

The automotive manufacturers now focus on some major capabilities like real-time vehicle-to-vehicle communication, vehicle-to-infrastructure, telematics,

Effectively managing a huge pool of electronic parts from various suppliers necessitates an in-depth understanding

The global market of  3D ICs was valued at US$ 7,521.4 Mn in 2019 and

What is LVS? In ASIC physical implementation, once layout is generated, it must follow all

To begin with, Value Analysis and Value Engineering help in gaining the right balance between