Blogs - Semiconductor
Power Dissipation in VLSI: Moving to Low Power SoC Design While Improving Performance
In this day and age, we need sleeker devices with more capabilities and longer battery life. This can be accomplished by packing more components on smaller chips, thus moving to low geometry chip design. However, power dissipation or leakage current occurs in all the circuits that are currently used, which increases the overall power consumption, making it less suitable for mobile applications. This blog talks about the types of power dissipation and also mentions the ways to prevent this voltage loss.
Correlation of Routability and Placement Density for better QoR in 16nm technology
In any physical design procedure, Placement and Routing are the two chief steps. To get
Evaluating Potential Business Benefits of FPGAs
As consumer demand keeps changing, manufacturers need to change or upgrade their product to stay relevant. FPGAs are designed to provide the required flexibility and make changes to the device functionalities at any point even after deployment at the customers’ end. This blog will discuss how FPGAs can provide noteworthy benefits to enterprises.
Low Power Design & Optimization using Multi BIT flops and MIMCAPs in 16nm technology and below
Power requirements are very critical in modern networking ASIC design. Robust power planning often undergoes
Smart Tracking of SoC Verification Progress Using Synopsys’ Hierarchical Verification Plan (HVP)
Introduction SoC (System-on-Chip) Verification effort mainly includes three key phases: Planning, Development and Verification. Planning
Ins and Outs of Assertion in Mixed Signal Verification
Introduction Assertion-based verification (ABV) is a powerful verification approach that has been proven to help
How to speed up the System-on-Chip (SoC) Functional Verification Flow?
1. SoC Level/Top Level view (Feature Extractions) During SoC design verification, you must view the
55 Semiconductor & Electronic Design Networks and Profiles to Follow in 2018
To gain knowledge and learn new things on professional front or to simply stay connected
Common Challenges of Lower-Technology Nodes for IoT Devices
In 1965, Gordon Moore, a co-founder of Intel, observed that the number of transistors per