Many designers are eager to build new products on multi-core processors. This blog is to identify applications for multi-core processors, and some key selection criterion to select the best platform suited to the application.
Multi-core processors are prescribed for compute-intensive and performance-demanding applications like Drones (Unmanned Aerial Vehicles), Radars, Storage, Graphics, and Servers; especially for data that requires high performance processing like Multimedia and Analytics. These applications need smart processing to analyze gigabytes of data in a matter of seconds. Further the analysis and response generated in fractions of seconds.
Using multiple Servers as in a distributed architecture is expensive, bulky and inefficient. The alternative lies with multi-core processors, as they come with a unique blend of DSP and ARMTM cores
The design can be done with various combinations of ARM and DSP processors. Depending on the application, one has to choose the right blend of ARM and DSP options. ARM cores provides efficient platform for Operating system, peripheral support and system control. DSP cores can handle the algorithms, complex calculations, and other data processing functions. Selecting the right blend will require some thought process. Imagine the processing power with dual 1.2Ghz ARM and Quad 1.2GHz DSPcores inside the same SoC.
Selecting the right platform is the most challenging task during system architecture phase. More often than not, requirements are updated midway during the designs. This added functionality affects the system performance or User Experience that might lead to a poor user experience when the product hits the market. Thus, one must consider a scalable platform so that if the design needs more power or features, one can easily migrate to a higher processing platform. For e.g. Edison (K2E) platform provides a series of SoC’s that you can use to upgrade the processing power
Nyquist’s Theorem, gives us a broad guideline about selection of right IO speeds. However, one also has to calculate the input and output bandwidths to ensure the processor is able to process the data at the same speed as is incoming data rate. Sooner or later, this is the primary cause for design spins.
Yes I have a Scalable platform. I can add more processing power by adding in more cores, more DSP’s, more CPU’s. Still my User experience or system performance is not yet there. More often than not, the reason is that although the processor is right, the memory options are not. This might be On-Chip memory (SRAM, L1/L2/L3 cache and so on) or it might be my DRAM (Size, Speed). Selection of right processor and memory is paramount for an efficient design.
Am I missing out on something more? Selection of the right processor and memory is necessary, but not sufficient. The way one implements and uses the memory is probably the more important aspect. This requires to storage of data in DRAM in an optimum manner that it is most likely to be read out. A lot of times, we have helped our clients in increasing the performance by using the memory in the right manner. Implementing DMA operations, partitioning the data and using the burst modes can help significantly.
With multi-core processors, carefully examine the design partition based on inter-core communication. This will help in load sharing and avoid bus latency due to bus unavailability. Separating out functions across the cores can bring in much higher performances. Easier said than done, this requires a thorough analysis to arrive at optimum design partition
Scheduling is one of the most important implementation criterion. The priorities of tasks should be carefully decided in ensuring optimum performances. A waiting high priority task is a waste of processor time. Use optimum concurrent processing to boost System performance. Using appropriate implementation techniques will help in boosting performance
Typically designers face the dilemma of calculating the power requirements of the processor even without knowing the MIPS utilized. Can we spin this paradigm and calculate the MIPS that can be delivered with the designed power? I leave it to you readers to decide. Every extra watt adds challenge to Thermal Dissipation as well.
This is Part 1 of a Two Part Series. The second part will cover three of the latest SoCs based on the TI’s Keystone devices being used in eInfochips. Stay Tuned.