Blogs - Semiconductor

June 18, 2019

Powering Design Innovations with Lower Technology Nodes at 7nm and Beyond [Infographic]

The developments in the past in chip design laid the foundation for lower technology nodes

Blog
June 4, 2019

ASIC Design Flow in VLSI Engineering Services – A Quick Guide

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

Blog
May 29, 2019

How Formal Verification Alleviates the Dark Sides of RISC-V Cores?

Verification is the process of reviewing, inspecting, or testing hardware design in order to get

Blog
April 26, 2019

Signoff Iteration Reduction Technique for Fixing Top Level Antenna

While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design,

Blog
April 25, 2019

Memory Testing: MBIST, BIRA & BISR | An Insight into Algorithms and Self Repair Mechanism

Typically, we see a 4X increase in memory size every 3 years to cater to

Blog
April 16, 2019

How to Deliver On-Time at Lower Technology Nodes (7nm,10nm,16nm…)?

Over the years, we have seen a wide range of advancements in semiconductor design services.

Blog
April 9, 2019

A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology

The intent of this paper is to explain the varied kinds of DRCs (Design Rule

Blog
April 4, 2019

Reducing DFT Footprints: A Case in Consumer SoC

Nowadays, placing multiple IPs on a single chip plays the most vital role in satisfying

Blog
March 25, 2019

Enhancing the Situational Awareness of Pilots with Voice Assistance

This article explores the role of voice messages for cockpit display systems in avionics. In

Blog

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