7 Tools to be consider in DFT Flow for IoT Device Design

7 Tools to be considered in DFT Flow for IoT...

Gartner says that more than 6.4 billion Internet of Things (IoT) devices will be in use in 2016, and that number will grow to more than 20 billion by…

why can’t the semiconductor industry afford to take its eyes off serdes

Why can’t the Semiconductor Industry afford to take its Eyes...

In this era of pervasive connectivity, everything needs to communicate with each other and everything around them by means of the internet. There is never-ending…

Top 5 Solutions for Optimal DFT (Design for Testability) in Lower Technology Nodes

Top 5 Solutions for Optimal DFT (Design for Testability) in...

Design for Testability (DFT), is one of the effective ways to overcome power consumption challenges and huge data volumes in the testing process after production,…

Powering Design Innovations with Lower Technology Nodes at 7nm and...

The developments in the past in chip design laid the foundation for lower technology nodes that will improve power, area, and cost function. At every…

ASIC Design Flow in VLSI Engineering Services

ASIC Design Flow in VLSI Engineering Services – A Quick...

Today, ASIC design flow is a very mature process in silicon turnkey design. The ASIC design flow and its various steps in VLSI engineering that…

RISC V and Formal Verification

How Formal Verification Alleviates the Dark Sides of RISC-V Cores?

Verification is the process of reviewing, inspecting, or testing hardware design in order to get the desired output. The whole process revolves around one question:…

Signoff Iteration Reduction Technique for Fixing Top Level Antenna

While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design, implementing each block individually, and stitching them together at the…

Memory Testing - An Insight into Algorithms and Self Repair Mechanism

Memory Testing: MBIST, BIRA & BISR | An Insight into...

Typically, we see a 4X increase in memory size every 3 years to cater to the needs of new generation IoT devices. Deep submicron devices…

How to Deliver On Time at Lower Technology Nodes

How to Deliver On-Time at Lower Technology Nodes (7nm,10nm,16nm…)?

Over the years, we have seen a wide range of advancements in semiconductor design services. The Semiconductor Industry Association (SIA) announced that the global semiconductor…

A Heuristic Approach to Fix Design Rule Check (DRC) Violations...

The intent of this paper is to explain the varied kinds of DRCs (Design Rule Checks) that are encountered in the Physical Design flow. This…