Synopsys

eInfochips is a Synopsys’ SystemVerilog Catalyst Program Partner. Through this partnership, eInfochips gains early access to Synopsys’ tools, platforms, and solutions which support the SystemVerilog assertions strengths and standard.

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eInfochips is also a member of VMM Catalyst Program that is aimed at accelerating the widespread adoption of the industry-leading VMM verification methodology for SystemVerilog. This combined initiative has enabled customers to migrate from legacy environment to achieve enhanced verification coverage and performance.

As a part of “Turnkey Lab” initiative, eInfochips plans to offer comprehensive spec to silicon(ASIC/FPGA) design and development offerings from its Dedicated Design Centre. eInfochips has expertise on Synopsys tool chain across different stages of semiconductor engineering design cycle.

Design

  • DC Ultra, Design Vision
  • HDL Compiler

Verification

  • Formality,
  • VCS-MX

Physical Design

  • tarRC, IC Validator & Compiler
  • PrimeRail, PrimeTime SI

Design for Testability

  • DFTMAX, DFT Compiler
  • TetraMAX

Get a complete implementation of the proven VMM verification methodology for SystemVerilog standards.