How to Deliver On Time at Lower Technology Nodes

How to Deliver On Time at Lower Technology Nodes

Over the years, we have seen a wide range of advancements in semiconductor design services. The Semiconductor Industry Association (SIA) announced that the global semiconductor…

A Heuristic Approach to Fix Design Rule Check (DRC) Violations...

The intent of this paper is to explain the varied kinds of DRCs (Design Rule Checks) that are encountered in the Physical Design flow. This…

Reducing DFT Footprints: A Case in Consumer SoC

Reducing DFT Footprints: A Case in Consumer SoC

Nowadays, placing multiple IPs on a single chip plays the most vital role in satisfying System on Chip ASIC specification requirements. Most of the time,…

Enhancing the Situational Awareness of Pilots with Voice Assistance

Enhancing the Situational Awareness of Pilots with Voice Assistance

This article explores the role of voice messages for cockpit display systems in avionics. In vehicle navigation systems like GPS, the voice guides the driver…

Low Power Design in ASIC Physical Design

Low Power Design – A Game Changer in ASIC Physical...

With the advent of personal computers and integrated circuits, the target has been to fit as many transistors as possible in one chip and make…

Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC

Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC

With advanced technology nodes, the SoCs are growing in density and gate count. This creates challenges regarding the testability, and more importantly, the test cost.…

A Guide on Logical Equivalence Checking

A Guide on Logical Equivalence Checking – Flow, Challenges, and...

Introduction The VLSI design cycle is divided into two phases: Front-end and Back-end. Front-end covers the architectural specifications, coding and verification, whereas back-end involves the…

Product Design Services for Intelligent Vending Machine Systems [Video Infographic]

Product Design Services for Intelligent Vending Machine Systems [Video Infographic]

Retail companies feel the need to improve the process and turnaround times for moving a product from supplier to customer i.e. storing, delivering and providing…

DFT Challenges for Phase-Shifted Functional Clocks

DFT Challenges for Phase-Shifted Functional Clocks

The use of mixed-signal processing is becoming vital among a wide variety of applications like telecommunication, networking, sensor chips, etc. In many designs, we have…

System Verilog Assertions Simplified

Abstract Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the…