Whitepaper/Publications
Crosstalk Effect on Lower Technology Nodes in Complex SOCs Design
Executive Summary Nowadays most of the current System-on-Chip (Soc) circuits used
January 6, 2023
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Services Category: ASIC/FPGA Design & Development
Whitepaper/Publications
A Guide on Logical Equivalence Checking
White Paper – This paper gives an introduction of logical equivalence check, flow setup, steps to debug it, and solutions to fix LEC…
March 26, 2019
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Case Study
Physical Design of Data Center ASIC
Case study – How we helped a niche data center infrastructure start-up with the Physical Design of an Innovative Data Center ASIC…
February 28, 2019
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Whitepaper/Publications
Multiple clock domain SoCs: Addressing structural defects
In the previous blog (Synchronization techniques for multi-clock domain SoCs & FPGAs), we studied different types of…
October 22, 2014
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Whitepaper/Publications
Synchronizer techniques for multi-clock domain SoCs & FPGAs
In general, a conventional two flip-flop synchronizer is used for synchronizing a single bit level signal…
September 30, 2014
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Case Study
Low Power Networking ASIC
This was one of the earliest design projects for 16nm geometry for the customer, a global data networking…
March 27, 2014
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Whitepaper/Publications
Exploring the Network on Chip Concept
SOC (System On Chip) and behavioral designs are integrating more systems and functions to meet market…
September 27, 2013
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Whitepaper/Publications
5 Simple Steps to Close Functional Coverage to 100%
This paper presents the way to close functional coverage to 100 per cent by following five simple steps…
June 14, 2013
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Whitepaper/Publications
FPGA Prototyping Trends and Challenges
As the cost per gate of FPGAs declines, embedded and high performance systems designers are being presented…
May 14, 2013
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