In the previous blog (Synchronization techniques for multi-clock domain SoCs & FPGAs), we studied different types of synchronization techniques to synchronize signals from one clock domain to another. Even when proper synchronization techniques are used in a multi-clock design, they are not sufficient to avoid all possible problems due to structural defects. Hence extra care must be taken by designers while applying these synchronization techniques in real designs. Some of the structural problems that may cause functional errors in multi-clock-based systems follow.

Input to any synchronizer must be output of a flip flop operating in source clock domain. As shown in Figure 1, if combinational output is directly fed to any synchronizer it may cause undesirable effects.