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In this blog, we will showcase how signal drive strength can be checked in SystemVerilog for best possible results, and the various rules which have to be observed in “documenting” signal strength.
According to basic principles of testing electronic systems, signal drive strength is considered one of the key metrics of signal integrity (SI). Whether you’re designing PCB, SoC, microcontroller, USB or any other electronic component, the ability to transmit the signal with high fidelity depends on signal drive strength. Drive strength can be used to resolve which value should appear on a net or gate output.
In a SystemVerilog test bench, it often happens that multiple drivers would try to drive a single net or output of gate. In this scenario, the output value is best determined based on the signal driving strength of each driver and its corresponding value.
The following table has been derived from a SystemVerilog test bench spelling out different drive strength examples, their naming conventions, and abbreviation. Supply strength is strongest and high is the weakest.
Figure 1: Strength based on value
It is important to be able to check drive strength on a wire for a particular instance. Here’s an example that helps illustrate that.
Figure 2: Checking drive strength for a particular instance
Any Gate (here we have taken example of buf) can be declared with drive strength as one of the following:
buf (strong1, weak0) #(10) b1 (out1, in1);
buf (weak0, strong1) #(10) b2 (out1, in1);
Or you can use assign statement as below:
assign (weak0, strong1) out1 = in1;
We can get the current value of drive strength using $sformatf and display it using %v
and (supply1, weak0) a1 (y,a,b);
str = $sformatf(“%v”, y);
$display(“Strength=%v Value=%b”, y, y);
Also, a few basic rules have to be kept in mind concerning signal drive strength.
If two drivers are driving a signal, then the signal with the strongest value will be considered
Figure 3: Signal with strongest value
If two drivers are of the same strength and value, then the signal strength will remain same.
Figure 4: Signal of same value
When multiple drivers are present, the output signal’s value and strength depends on strength and values of all the drivers. See table below.