AMSify
A Novel Mixed-Signal Verification Methodology
AMSify is a Mixed-Signal verification methodology using SV-UVM. It includes state-of-the art technique in Mixed-Signal design simulation to determine to which extent current simulation technologies can effectively support the design process.
Benefits
- Supports any mixed-signal design verification project using batch mode simulation.
- Re-use digital SV-UVM test bench components for AMS verification
- Automated methodology development using scripts
Verification Test-bench Architecture of POR Using AMSify Methodology
Power on Reset Verification Using AMSify Methodology
This methodology has the feature to generate controlled custom signal either in analog or in digital kernel based upon the necessity and is modelled using Verilog-AMS, a de facto official language for Mixed-Signal modelling. The signal parameters e.g. frequency, amplitude, offset etc., can be controlled by the UVM test bench.
