DAeRT (Dft Automated execution and Reporting Tool) is a frame work that gives a platform to create DFT (Design For Testability) flow. DAeRT enables to achieve ~100% testability for the ASIC designs. “DAeRT” supports various DFT methodologies starting with IJTAG/JTAG, MBIST, Scan, ATPG, Pattern Validation, Test Timing Analysis and Post-Si validation. It also support Synthesis. DAeRT is a solid frame work tool that can be enhanced and ported for various DFT flows.
DAeRT stages mentioned in the Figure – 1 can perform independently to implement different stages of ASIC DFT cycle parallel to each other. Each stage has different flow chart and its unique features.
DAeRT provides GUI and Non-GUI based support to fill required input data. Review of Logs and reports are made easy for lead/managers by a summarized HTML page which would take all data implemented and highlight it if there is any risk.
At the end of execution of entire DAeRT flow, the design would have JTAG insertion, MBIST insertion, Scan insertion, Formal verification, ATPG on various fault models, Pattern validation, Test constraint generation and its validation.