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Towards a Green Future with eInfochips
Towards a Green Future with eInfochips
Nilesh Ranpura
October 1, 2015
Nilesh Ranpura
With 14+ years of experience in VLSI Design Cycle, Methodologies, Project execution and ODC set up Nilesh has participated in multiple projects for Verification, Physical design, DFT in the area of bus interface and Networking domain for Multi-million gate count SoC. His specialization is on ASIC product development and ODC growth solutions.
Implementation Challenges for Large 28nm SoCs
Recently I was interviewed by Brian Fuller in ‘The Fuller View’ at Cadence. I am
Nilesh Ranpura
March 10, 2015
