UVM Verification Framework for Optical Network SoC
The increasing complexity of Networking SoC both in terms of size and the increased level of interaction…
SRIO GEN2 Buffer Management
The Serial RapidIO (SRIO) Gen 2.2 protocol is an energy-efficient and high-performance interconnect protocol designed…
Verification Approach Towards an Evolving IP
INTRODUCTION: Universal Flash storage (UFS) is an upcoming JEDEC standard primarily targeted for mobile systems…
Multiple clock domain SoCs: Verification techniques
EDA tool vendors provide various solutions to check whether proper implementation of CDC is done or not. EDA vendors like Synopsys, Atrenta, Mentor, and Cadence
Common Constraints Considerations in SystemVerilog
Everyone is talking about Coverage Driven Verification and everyone wants go random. Randomization leads to…
Bridging the Gap: Pre to Post Silicon Functional Validation
Post silicon validation is a vital phase of verification that deals with verification after the real silicon is in place…
