Executive Summary
Universal Verification Methodology-System Verilog based Verification Frame is a reusable verification solution for functional verification and co-simulation of SoCs used in Networking device applications like SoCs for Long Haul (between inter-continentals) and Data Centre applications. UVM-System Verilog based Verification framework consists of verification components for Digital Stimulus generation and monitoring, functional accurate behavioral models for Digital circuits, protocol checks for various interfaces, Test bench setup, Test scenarios and transaction level data checkers for various data paths.
Project Highlights
- Reusable verification components from block level to Top level
- Effective verification of Digital Controls circuit and detection
- Constrain random stimulus provides better verification coverage for various control combinations and stimulus
- Self-checking and transaction level interaction ensure easier and faster absorption of recurring Digital circuit
