UVM Verification Framework for Optical Network SoC

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UVM Verification Framework for Optical Network SoC

Summary

Universal Verification Methodology-System Verilog based Verification Frame is a reusable verification solution for functional verification and co-simulation of SoCs used in Networking device applications like SoCs for Long Haul (between inter-continentals) and Data Centre applications. UVM-System Verilog based Verification framework consists of verification components for Digital Stimulus generation and monitoring, functional accurate behavioral models for Digital circuits, protocol checks for various interfaces, Test bench setup, Test scenarios and transaction level data checkers for various data paths.

Benefits

  • Reusable verification components from block level to Top level
  • Effective verification of Digital Controls circuit and detection
  • Constrain random stimulus provides better verification coverage for various control combinations and stimulus
  • Self-checking and transaction level interaction ensure easier and faster absorption of recurring Digital circuit

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    Summary

    Universal Verification Methodology-System Verilog based Verification Frame is a reusable verification solution for functional verification and co-simulation of SoCs used in Networking device applications like SoCs for Long Haul (between inter-continentals) and Data Centre applications. UVM-System Verilog based Verification framework consists of verification components for Digital Stimulus generation and monitoring, functional accurate behavioral models for Digital circuits, protocol checks for various interfaces, Test bench setup, Test scenarios and transaction level data checkers for various data paths.

    Project Highlights

    • Reusable verification components from block level to Top level
    • Effective verification of Digital Controls circuit and detection
    • Constrain random stimulus provides better verification coverage for various control combinations and stimulus
    • Self-checking and transaction level interaction ensure easier and faster absorption of recurring Digital circuit

    To read more, download the copy

    arrows-new-1

    To download this resource

    Fill in the details below






      I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

      I wish to be contacted by eInfochips I wish to be contacted by eInfochips

      For all career related inquiries, kindly visit our careers page or write to career@einfochips.com

      Summary

      Universal Verification Methodology-System Verilog based Verification Frame is a reusable verification solution for functional verification and co-simulation of SoCs used in Networking device applications like SoCs for Long Haul (between inter-continentals) and Data Centre applications. UVM-System Verilog based Verification framework consists of verification components for Digital Stimulus generation and monitoring, functional accurate behavioral models for Digital circuits, protocol checks for various interfaces, Test bench setup, Test scenarios and transaction level data checkers for various data paths.

      Project Highlights

      • Reusable verification components from block level to Top level
      • Effective verification of Digital Controls circuit and detection
      • Constrain random stimulus provides better verification coverage for various control combinations and stimulus
      • Self-checking and transaction level interaction ensure easier and faster absorption of recurring Digital circuit

      To read more, download the copy

      arrows-new-1

      To download this resource

      Fill in the details below






        I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

        I wish to be contacted by eInfochips I wish to be contacted by eInfochips

        For all career related inquiries, kindly visit our careers page or write to career@einfochips.com