Multiple clock domain SoCs: Verification techniques

Executive Summary

With technology advancement and introduction of more complex SOCs, data transfer between multiple clock domains is more frequent and demanding, and CDC design and verification becomes a more challenging task. An understanding of metastability plays a key role in understanding CDC problems and associated design challenges. Adoption of new verification techniques in the early stages also plays an important role in easing and speeding up multi-clock domain design and verification activities.

Project Highlights

EDA tool vendors provide various solutions to check whether proper implementation of CDC is done or not. EDA vendors like Synopsys, Atrenta, Mentor, and Cadence provide solutions through simulation, Linting, and LEC.
To Download This Resource
Fill in the details below
By submitting this form, I acknowledge that I have read and understand the Privacy Policy
I wish to be contacted by eInfochips

Our Work





Device Partnerships
Digital Partnerships
Quality Partnerships
Silicon Partnerships


Products & IPs