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X-Propagation Simulation: A Powerful Feature
An Overview In VLSI design, “verification” is a crucial step to verify the correctness and
Abhay Sonagara
June 15, 2026
Abhay Sonagara is an ASIC Verification Senior Engineer – Level 1 at eInfochips, an Arrow company. He specializes in the functional verification of ASIC, IP, FPGA, and SoC designs, ensuring bug-free RTL delivery through efficient testbench development techniques, exhaustive verification plan, and comprehensive test scenario creation for DV simulations. He has over 4.5 years of experience in the functional design verification of various RTL designs.
He has developed the testbenches from scratch and modified them too, including UVM components like UVC, monitor, driver, reference model, scoreboard, and agents. He also has hands-on experience with code and functional coverage metrics, assertions, VIP integration, X-prop, and gate level simulations.
An Overview In VLSI design, “verification” is a crucial step to verify the correctness and
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