Functional Verification of Next-Generation RF Based Automatic Test Equipment

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Functional Verification of Next-Generation RF Based Automatic Test Equipment

Executive Summary

The client is a developer and supplier of automatic test equipment (ATE) that are used by leading tier-1  and tier-2 semiconductor customers for testing their next-gen chips. With the increase in complexity of the chips, the cost and time of testing them has increased exponentially. The client’s ATE instruments help automate two of manufacturing’s most critical elements: repetitive manual tasks and electronic tests. The ATEs are used to test chips of all sizes, applications, and for varied market demands, to ensure that these chips perform as per the design requirements. These chips are reshaping markets where innovation is assumed, and failure is not an option.

The client’s ATEs are based on the latest FPGA platforms to cater to high-end computing & performance requirements and also for legacy hardware. They were looking for a partner who is an expert in functional verification of complex ASICs and FPGAs. eInfochips took the complete ownership of the functional verification of the client’s FPGA based ATE. eInfochips developed a verification environment with reusable components to meet the stringent technical and timeline requirements.

Project Highlights

  • Configurable I/O
  • Complex DSP Blocks
  • High Data Rate – 1 Giga Samples/Second
  • Proprietory Complex Blocks for TX & RX

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Executive Summary

The client is a developer and supplier of automatic test equipment (ATE) that are used by leading tier-1  and tier-2 semiconductor customers for testing their next-gen chips. With the increase in complexity of the chips, the cost and time of testing them has increased exponentially. The client’s ATE instruments help automate two of manufacturing’s most critical elements: repetitive manual tasks and electronic tests. The ATEs are used to test chips of all sizes, applications, and for varied market demands, to ensure that these chips perform as per the design requirements. These chips are reshaping markets where innovation is assumed, and failure is not an option.

The client’s ATEs are based on the latest FPGA platforms to cater to high-end computing & performance requirements and also for legacy hardware. They were looking for a partner who is an expert in functional verification of complex ASICs and FPGAs. eInfochips took the complete ownership of the functional verification of the client’s FPGA based ATE. eInfochips developed a verification environment with reusable components to meet the stringent technical and timeline requirements.

Project Highlights

  • Configurable I/O
  • Complex DSP Blocks
  • High Data Rate – 1 Giga Samples/Second
  • Proprietory Complex Blocks for TX & RX

To read more, download the copy

arrows-new-1

To download this resource

Fill in the details below





I wish to be contacted by eInfochips

Executive Summary

The client is a developer and supplier of automatic test equipment (ATE) that are used by leading tier-1  and tier-2 semiconductor customers for testing their next-gen chips. With the increase in complexity of the chips, the cost and time of testing them has increased exponentially. The client’s ATE instruments help automate two of manufacturing’s most critical elements: repetitive manual tasks and electronic tests. The ATEs are used to test chips of all sizes, applications, and for varied market demands, to ensure that these chips perform as per the design requirements. These chips are reshaping markets where innovation is assumed, and failure is not an option.

The client’s ATEs are based on the latest FPGA platforms to cater to high-end computing & performance requirements and also for legacy hardware. They were looking for a partner who is an expert in functional verification of complex ASICs and FPGAs. eInfochips took the complete ownership of the functional verification of the client’s FPGA based ATE. eInfochips developed a verification environment with reusable components to meet the stringent technical and timeline requirements.

Project Highlights

  • Configurable I/O
  • Complex DSP Blocks
  • High Data Rate – 1 Giga Samples/Second
  • Proprietory Complex Blocks for TX & RX

To read more, download the copy

arrows-new-1

To download this resource

Fill in the details below





I wish to be contacted by eInfochips