Executive summary
A Machine Learning SoC program requires an early system‑level validation to ensure smooth integration across the compute, memory, interconnect, and peripheral subsystems. The design included high ‑performance blocks such as HBM, PCIe, and NoC, along with ARM debug trace and ‑low bandwidth peripherals.
Hardware emulation was used to accelerate pre‑silicon ‑bring up and enable early visibility into boot behavior, register access, peripheral communication, and subsystem interactions. By establishing a structured emulation framework, the program reduced integration risk and improved readiness ahead of silicon availability.
Key Highlights
- Machine Learning SoC emulation for complex subsystem validation
- Support for HBM, PCIe, NoC, ARM debug trace, and peripheral subsystems
- Validation performed on Palladium and Zebu emulation platforms
- Python driven JTAG access for register, memory, and SoC bring up
- BFMs developed for SPI, I2C, and UART peripheral verification
- C‑based tests for boot, peripheral access, and subsystem validation
