Effective PHY Verification of High Bandwidth Memory (HBM) Sub-system

Executive Summary

Memory systems have improved a lot in the past few years owing to increasing data digitization and advancements in fabrication technology. High Bandwidth Memory (HBM) is an example of a new kind of memory chip designed to support low power consumption, ultrawide communication lanes and the latest advances in stacked configurations. HBM’s vertical stacking and fast information transfer rates can lead to some truly astounding performance rates across different, innovative form factors. It is ideally suited for high performance graphics and computing applications, high-end networking/communication devices and memory-hungry processors.

The eInfochips client, being an early adopter of HBM, wanted to introduce the technology to its newly launched storage solution, with in-built support for multiple memory controllers (full speed, half speed), HBM PHY and HBM DRAM. The client, however, was facing struggles in the verification of the HBM PHY layer due to the lack of an effective verification strategy and stringent delivery deadlines for multiple end customers. eInfochips introduced a verification strategy for the client to support the entire block and full-chip verification on HBM physical layer, meeting timelines while supporting 3 design releases and more than 5 end customers.

Project Highlights

    • Block & Full Chip Verification
    • 50+ Bugs found in Preverified
    • Controllers and Memory Models
    • 3+ Design Releases, On time
    • 5+ End Customers Supported
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