It is extremely difficult to design analog mixed-signal circuits capable of handling speeds of 28 Gbps or greater. To achieve a low jitter, good clock recovery, and signal integrity across process, voltage, and temperature corners need an in-depth understanding of SerDes PHY development and post-layout verification.

The client-a leading semiconductor company was looking for end-to-end support in developing a high-speed SerDes PHY IP that supported PCIe Gen4 and Passive Optical Network (PON) protocols. The requirement of the design was to achieve a reliable transmission speed from 1 Gbps to 28 Gbps on a TSMC 16nm node.

Apart from meeting the bandwidth objective, there were critical additional challenges to be addressed, including maintaining signal integrity through equalization, ensuring accurate clock data recovery, and achieving seamless integration between the transmitting and receiving chains. Solving such challenges requires proven silicon engineering expertise as well as a systematic approach to design, layout, and testing.

eInfochips, with its expertise in analog/mixed-signal design, verification, and IP migration services, took complete ownership of the project. Along with a dedicated team of engineers and proven design and verification platforms, the team was able to deliver a production-ready Serdes PHY IP supporting PCIe Gen4 and PON protocols that not only met performance requirements but also reduced risk with the help of rigorous post-layout verification, process-voltage-temperature closure, and silicon characterization.