UVM-MS Verification Framework for Mixed Signal SoC
Summary
Universal Verification Methodology-Mixed Signal Verification Frame is a reusable verification solution for functional verification and co-simulation of Mixed Signal SoCs used in sensor based smart device applications like IoT, Automotive and ICT (Information and Communication Technology) and ATE (Automatic Test Equipment). UVM is a proven functional verification methodology and UVM-MS methodology used by this framework is a customization and extension of UVM methodology to support Analog Designs and Mixed Signal interfaces used inside Mixed Signal SoCs.
Benefits
- Identify digital analog boundary interaction-related issues in early part of the functional verification
- Perform effective verification of Digital Controls of Analog circuit and detection of possible circular dependencies between Digital controls and Analog circuit states
- Constrain random stimulus to provide better verification coverage for various control combinations and Analog stimulus
- Achieve self-checking and transaction level interaction to ensure easier and faster absorption of recurring Analog circuit changes owing to correct verification nature of Analog design flow
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The buck stops here. CloudOps
Universal Verification Methodology-Mixed Signal Verification Frame is a reusable verification solution for functional verification and co-simulation of Mixed Signal SoCs used in sensor based smart device applications like IoT, Automotive and ICT (Information and Communication Technology) and ATE (Automatic Test Equipment). UVM is a proven functional verification methodology and UVM-MS methodology used by this framework is a customization and extension of UVM methodology to support Analog Designs and Mixed Signal interfaces used inside Mixed Signal SoCs.
Project Highlights
- Identify digital analog boundary interaction-related issues in early part of the functional verification
- Perform effective verification of Digital Controls of Analog circuit and detection of possible circular dependencies between Digital controls and Analog circuit states
- Constrain random stimulus to provide better verification coverage for various control combinations and Analog stimulus
- Achieve self-checking and transaction level interaction to ensure easier and faster absorption of recurring Analog circuit changes owing to correct verification nature of Analog design flow
To download this resource
Fill in the details below
The buck stops here. CloudOps
Universal Verification Methodology-Mixed Signal Verification Frame is a reusable verification solution for functional verification and co-simulation of Mixed Signal SoCs used in sensor based smart device applications like IoT, Automotive and ICT (Information and Communication Technology) and ATE (Automatic Test Equipment). UVM is a proven functional verification methodology and UVM-MS methodology used by this framework is a customization and extension of UVM methodology to support Analog Designs and Mixed Signal interfaces used inside Mixed Signal SoCs.
Project Highlights
- Identify digital analog boundary interaction-related issues in early part of the functional verification
- Perform effective verification of Digital Controls of Analog circuit and detection of possible circular dependencies between Digital controls and Analog circuit states
- Constrain random stimulus to provide better verification coverage for various control combinations and Analog stimulus
- Achieve self-checking and transaction level interaction to ensure easier and faster absorption of recurring Analog circuit changes owing to correct verification nature of Analog design flow
To download this resource
Fill in the details below