Synchronizer techniques for multi-clock domain SoCs & FPGAs

Executive Summary

In general, a conventional two flip-flop synchronizer is used for synchronizing a single bit level signal. As shown in Figure 1 and Figure 2, flip flop A and B1 are operating in asynchronous clock domain. There is probability that while sampling the input B1-d by flip flop B1 in CLK_B clock domain, output B1-q may go into metastable state. But during the one clock cycle period of CLK_B clock, output B1- q may settle to some stable value. Output of flop B2 can go to metastable if B1 does not settle to stable value during one clock cycle, but probability for B2 to be metastable for a complete destination clock cycle is very close to zero.

Project Highlights

A greater number of flop stages may be used if frequency is too high as it will help in reducing the probability of synchronizer output to remain in metastable state.
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