Physical Design Implementation Challenges in Highly Memory-Intensive Design in 40 nm

Executive Summary

Memory-intensive blocks with vivid aspect-ratio memory lead to tight challenges in floor planning to placement in terms of congestion and timing. This article discusses a methodology developed to overcome challenges in implementing a flat design with 1.6 million instances and 640 macros. It also talks about specific timing, congestion and power related challenges from floor planning to power planning stages, and different placement techniques adopted to overcome congestion and timing.

Project Highlights

Physical design implementation of a very large floor plan with high memory count poses multiple challenges mostly in areas like floor planning, power planning and also turnaround time for tool coupled with memory management.
To Download This Resource
Fill in the details below
By submitting this form, I acknowledge that I have read and understand the Privacy Policy
I wish to be contacted by eInfochips

Our Work





Device Partnerships
Digital Partnerships
Quality Partnerships
Silicon Partnerships


Products & IPs