Physical Design Implementation Challenges in Highly Memory-Intensive Design in 40 nm

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Physical Design Implementation Challenges in Highly Memory-Intensive Design in 40 nm

Description

Memory-intensive blocks with vivid aspect-ratio memory lead to tight challenges in floor planning to placement in terms of congestion and timing. This article discusses a methodology developed to overcome challenges in implementing a flat design with 1.6 million instances and 640 macros. It also talks about specific timing, congestion and power related challenges from floor planning to power planning stages, and different placement techniques adopted to overcome congestion and timing.

Publications

Physical design implementation of a very large floor plan with high memory count poses multiple challenges mostly in areas like floor planning, power planning and also turnaround time for tool coupled with memory management.

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Description

Memory-intensive blocks with vivid aspect-ratio memory lead to tight challenges in floor planning to placement in terms of congestion and timing. This article discusses a methodology developed to overcome challenges in implementing a flat design with 1.6 million instances and 640 macros. It also talks about specific timing, congestion and power related challenges from floor planning and power planning stages, and different placement techniques adopted to overcome congestion and timing.

Physical design implementation of a very large floor plan with high memory count poses multiple challenges mostly in areas like floor planning, power planning and also turnaround time for tool coupled with memory management.

Publications

To read more, download the copy

arrows-new-1

To download this resource

Fill in the details below





I wish to be contacted by eInfochips

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