Leakage power optimization for 28nm and beyond

Executive Summary

As process nodes shrink towards nanotechnology, the supply voltage is scaled down to protect the device from excessive electric field across the gate oxide and the conducting channel. Another reason for supply voltage reduction is to save dynamic power dissipation. On the flip side, this voltage reduction slows down the CMOS transistor.
To overcome this performance loss, the transistors’ threshold voltage is decreased, which increases sub-threshold leakage current. At these nodes, leakage power can contribute more than 50% of the overall chip power – hence, high performance chips have excess power dissipation, even in standby mode. Increasing performance causes more leakage power dissipation.
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