Executive Summary
In new era of chip implementation, designs are becoming more complex and challenging as technology is shrinking to 28nm and below. In advance technology process, the cell delays got reduced but impact of wire/via resistance becomes more critical than previous nodes as wire width is reducing. The larger wire delay affects transition time and yields poor timing in clock tree cause lower performance in physical implementation. With advance technology such as 28nm and below, the prices characteristics become remarkably complex and wiring resistance rapidly increases , which unavoidably means that more sign-off corners and more accurate sign-off and layout tools are required. This article illustrates how wire delay causes skew/timing problems when you are optimizing multi-corner design and how wire resistance can be optimized to achieve best performance during the physical implementation flow.
Multi-corner variation due to wire resistance
While optimizing design for MMMC (Multi mode multi corner), we usually see many discrepancies in timing scenario, it is not the case now that meeting design in hold best corners will meet in the hold worst with same temperature. In fact we might see more timing violation in hold-worst corner than hold-best. One of the main parameter is wire resistance because slow path in hold-best corner could be faster in hold-worst due to wire delay difference.
