As technology shrinks, Yield and Reliability (YAR) are major challenges of SoC (System on Chip) production. There are many techniques available for increasing YAR. YAR of devices depend on testing strategies and the effectiveness of a testing methodology. (Design for Testing) DFT’s main challenge is how to improve YAR; this paper describes the yield improvement by specifically using current testing. IDDQ testing (IDT) is a novel approach for testing faults which are left undetected by voltage testing. IDT is an essential quality testing requirement for today’s deep submicron devices (DSM) and Very deep submicron devices (VDSM).

In order to achieve high quality VLSI chips, you must employ a rigorous testing strategy. Design for testing is one of the major challenges in VDSM technologies. There are many different testing techniques available such as Stuck-At (SA), Delay, functional, IDT and Burn-In testing.